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Project Name

Integrated Circuits – Center of Excellence

Department

Electronics & Telecommunications Engineering

Project Lead from the Department

Prof. Sayan Chatterjee

Faculty

Faculty of Engineering and Technology

Project Lead from GJUAF

Dr. Shubhankar Basu

Overview

What Is the Integrated Circuits Center of Excellence?

The Integrated Circuits Center of Excellence is founded on an idea of collaborative multidisciplinary research by students and faculties of Jadavpur University, which is housed in the Electronics and Telecommunication Engineering Department at Prayukti Bhavan. The objective of the COE is to train students to produce job and higher studies ready skill sets and hands-on training in collaboration with leading industry partners, global academic institutions, and research labs. Building new labs and upgrading existing infrastructure with new equipment, new software and new hardware capabilities is one of the primary objectives to create a framework for state-of-the-art learning and research. Starting with the second-year undergraduate students to PhD scholars, the IC COE aims to facilitate activities in the areas of Integrated Circuits design, VLSI CAD tool development, IoT system design, Artificial Intelligence and Machine Learning (data science) applications research and Analog and RF circuits design. 

Request for funding

USD 60,000

Budget

USD 140,000 (for 3 years – Subject to Performance Evaluation)

Quote from vendors

Synopsys (software), Computer Systems, Embedded Systems GPUs, etc.

Funds Transferred

USD 31,750

Fund Distributed to date

INR 24,50,000

Procurement status

As of June 2024: (Delay due to administrative issues at JU – Moving now)

  • JU Purchasing has sent a purchase order to Synopsys for software to support Analog & Mixed Signal Laboratory.
  • JU FO and Purchasing department in the process of raising tenders for 19 computers for Analog & Mixed Signal Laboratory.
  • JU FO and Purchasing department in the process of raising tender for GPUs for IoT and Embedded systems Laboratory.
  • Purchased 1 workstation, switches required for EDA software in the labs.
  • Donation of software licenses via Synopsys Sponsorship completed in Aug 2023.

Completed or expected completion date

September 2024

Remaining budget for this project

USD 5,938

Benefits to students and JU

IC COE Program Benefits

There are several expected benefits from the IC COE initiatives at Jadavpur University: 

  • Position Jadavpur University as the nodal hub for semiconductor learning in eastern India. 
  • JU being able to train over 200 students each year from the university as well as from other institutes and industry in eastern India by offering formal training courses. 
  • Ability to secure guided PhD research and UG/PG sponsored projects from industry collaborators.
  • Ability to secure internships and campus hire from industry partners on a continuous basis. 
  • Ability to win Department of Science and Technology (DST) and Ministry of Electronics and Information Technology (MEiTY) sponsored projects for advancing research and securing JRF/SRF fellowship awards. 
  • Ability to actively participate in leading National and International conferences through Paper/Poster submission acceptance. 
  • Ability to compete and win National Competitions in the identified areas of focus. 
  • Launch several focused Student Clubs and attract students from across the university to participate in interdisciplinary projects. 
  • Accelerate the Intellectual Property capabilities of JU. 
  • Foster innovation and launch of startups from JU research.

Commendation letters including the receipt of equipment or services from the Head of the Departments: Attached

 

Photos: https://iccoe-jadavpuruniversity.in/

Project Status

Work Planned for the project:

Year One (2024) Goals

  • Win at least 2 research grants from DST/MEITY/Joint calls:
    • C2S (Top priority) -> Partially won: JU has been selected to be granted access to EDA tools from CDAC at no cost.
    • One other among: DST (Water), DST (Senior Citizen Health), Indo-Taiwan (WPC), DST-NSF (CVD + UPC).
    • Win smart agriculture project grant from DST if it opens.
    • Any other similar grants that we may apply for.
  • Set up at least 4 paid JRF/SRF fellowship funds for hiring 4 paid full-time PhD students.
  • Synopsys Digital VLSI Laboratory (Done)
  • Analog-Mixed Signal VLSI Laboratory. (WIP)
  • IoT/AI-ML Laboratory equipped with computers and embedded system design and test equipment. (Done)
  • MoU completion with GF (Done), SNPS (Done), HCL (Done), UTL (Done), Ansys (Not required as acquired by SNPS).
  • MoU completion with IMEC (WIP).
  • Launch Digital VLSI Club (Launched), IoT System Design Club, Al Club, Mechatronics Club (launched)
  • Launch group of 8 faculty club representing all departments in JU (Done).
  • Curriculum changed to facilitate corporate partners' requirements + modern practical education in line with AICTE regulations. (WIP)

HCL sponsored Project and Internship  -> Initiated

Internships that need to be started:

  • Juniper → Started
  • Globalfoundries → Started
  • Synopsys
  • Qualcomm
  • IMEC

Students training on Processor Design:

Focus on RISC-V design

Industrial visits:

Juniper, HCL, TCG-Crest, SNPS (Bhubaneswar), Schneider, Siemens EDA, IBM, CDNS, Ansys, others.

Campus recruitments:

Try to bring QCOM, CDNS, SNPS, Siemens EDA, Nvidia, AMD, ARM, Analog Devices, HCL, Juniper, Cisco, Google, Meta, LinkedIn, MSFT, others on campus.

Set up research and student collaboration with 5 different global universities:

Georgia Tech, Arizona State University, National Tech University (Singapore), UT Dallas, IISc.

Media Coverage:

Get covered at VLSI Design Conference, Get covered by National Times of India, Get covered by regional TOI, Telegraph, ABP, etc.

Bring USD 60,000 funding from Global Alumni

  • Work performed during this period - Identified above.
  • Percentage of work completed - 70% (Main hold up with the purchase order and procurement delays in the university administration)

Financial Status

  • Budget for the project:  3 year budget USD 140,000; First year budget USD 60,000.
  • Total Donation received: USD 40,675 (Combining US and India based donations).
  • Expensed to-date: USD 34,737 (received by FO); USD 0 (expensed so far due to Purchase Order holdup)
  • Percentage of the donation expensed: 85% (based on money transferred to FO); 0% (based on funds used to procure infrastructure)
  • Remaining donation to-date:  USD 5,938

Future Work

  • Work to be accomplished during the next 6 months:  Complete bring up of Analog & Mixed Signal VLSI Laboratory, Complete upgrade of the IoT, Embedded Systems and AI/ML laboratory infrastructure, Launch the students’ projects with HCL and Globalfoundries.
  • Estimated expense during the next 6 months: USD 40,675
  • Donation needed for the next 6 months: None.